1. Field of the Invention
This invention relates generally to the field of digital data communication equipment, and more particularly to communication equipment which interfaces two networks, one transmitting data asynchronously and another transmitting data synchronously.
2. Description of the Prior Art
In the prior art of generating a parallel DS3 AIS signal, a DS3 clock is synthesized or a local oscillator is used to generate a DS3 clock. (The acronym "DS3" is the American National Standard Institute designation for a Digital Signal, Level 3.) The clock is then divided by five or by eight to latch five and eight bit words that make up a DS3 frame into a parallel to serial convertor. The serial output is used as is, or it is divided up again into eight bit bytes to be formatted into a DS3 payload.
The major shortcoming with this method is that an alternate DS3 clock must be generated whenever the normal clock fails. A DS3 clock failure or data failure requires a second clock to be used to generate the Alarm Indication Signal (AIS). A framed DS3 AIS payload must be created and passed to the next stage in place of the normal DS3 data.
The specific shortcomings with the method named above is that an extra clock generator or oscillator circuit is required to produce a divided down DS3 parallel clock of the correct frequency to generate continuous DS3 framed data.